name---->D2(字串長度:2)---->趙佑錫 Erick Chao (Cadence)(字串長度:30)```hide---->0(字串長度:1)---->0
(字串長度:2)```name2---->session(字串長度:7)---->Erick Chao(字串長度:10)```talk_title---->(字串長度:0)---->The Evolution of AI in Chip Design(字串長度:34)```talk_lang---->(字串長度:0)---->中文(字串長度:6)```can_playback---->(字串長度:0)---->yes(字串長度:3)```company---->10:30-11:00(字串長度:11)---->Cadence Design Systems(字串長度:22)```position---->53(字串長度:2)---->職稱47(字串長度:8)```company2---->AI(字串長度:2)---->ML INFRA(字串長度:8)```position2---->伊雲谷 (待確認)(字串長度:21)---->職稱二47(字串長度:11)```desc---->(字串長度:0)---->摘要47(字串長度:8)```me_desc---->(字串長度:0)---->With 23 years of extensive experience in IC design, implementation, and EDA development, I have a profound understanding of user requirements and software development in Electronic Design Automation (EDA). My journey in AI/ML began with graduation from the 1st Hsinchu manager class at Taiwan AI Academy (AIA). At the same time, I assumed a role as a ML architect within a top number 1 IC fabless company in Taiwan. Transitioning to Cadence Design Systems, I took the role of leading RD team in both Hsinchu and Shanghai. My perspective is all-encompassing, spanning from that of an adept end-user to that of a contributor to EDA solution development empowered by AI/ML technologies. At present, I am entrusted with the leadership of one of Cerebrus RD teams, a division responsible for the AI-driven production within Cadence Design Systems.(字串長度:842)```conf---->R2(字串長度:2)---->AI(字串長度:2)